Japanese Patent Application Laid-Open Publication No. 2001-358287 (Patent Document 1) discloses a structure of a chip-stacked semiconductor device in which a rear surface of a first semiconductor chip is exposed on the same plane as a sealing resin surface in a resin-molded state.
Also, Japanese Patent Application Laid-Open Publication No. 2003-318360 (Patent Document 2) discloses a structure of a non-lead type semiconductor device including a sealing member made of insulating resin, a tab on which a semiconductor chip is mounted, a plurality of leads, each having one surface exposed on a mounting surface of the sealing member, a first semiconductor chip supported on one surface of the tab, and a second semiconductor chip stacked and mounted on the first semiconductor chip, in which one surface of the tab is exposed on the mounting surface of the sealing member.
Moreover, Japanese Patent Application Laid-Open Publication No. 2002-26233 (Patent Document 3) discloses a structure of a semiconductor device including a first semiconductor chip and a second semiconductor chip that are mutually stacked and electrically connected with each other, in which a first die pad on which the first semiconductor chip is fixed and a second die pad on which the second semiconductor chip is fixed are provided and portions of the first die pad and the second die pad are exposed.